Design of Low Power Double Tail Comparator using CMOS Technology
|Research Area:||Volume 5,Issue 6, Nov. 2016||Year:||2016|
|Type of Publication:||Article||Keywords:||Analog to digital Converters, Proposed Double Tail Comparator|
The need for low-power, area efficient and high speed analog-to-digital converters is pushing toward the use of proposed dynamic double tail comparator to maximize speed and power efficiency. In this paper, the layout of proposed double tail comparator is designed using Microwind3.1 version and compiled for desired results. In DSCH3.1 version the Schematic of proposed comparator is runned. From these designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 90nm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced.
Full text: IJEIR_2162_FINAL.pdf