Low Power Design Using Adiabatic 2:1 MUX

Research Area: Volume 6,Issue 1, Jan. 2017 Year: 2017
Type of Publication: Article Keywords: Adiabatic, CMOS, PFAL, ECRL
Authors:
  • Smita Jagtap
  • Sandip Nemade
Journal: IJEIR Volume: 6
Number: 1 Pages: 23-25
Month: January
ISSN: 2277-5668
Abstract:
A conventional CMOS logic circuit design approach depends upon charging the output capacitive nodes to the supply voltage or discharging it to the ground. This is one of the most used methods in VLSI designs. There are various techniques to design low power circuits both at system level as well as at circuit level to reduce power consumption. One of the major source of power dissipation is the charging and discharging of capacitor. Adiabatic circuits use the above two methods viz. slow charging of capacitor and discharging, and recycling of charge to minimize the power consumed. Several Adiabatic designs have been designed and tested in this paper. The technology used for simulation is 180 nm CMOS technology with 5v power supply. The input data rate for CMOS is made identical to that of adiabatic circuit. The comparison requires developing the circuit schematic based on both static CMOS and PFAL technique. Each circuit is simulated for different frequency and corresponding dynamic power is calculated through the tool Multisim V11.

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