Parametric Optimization of Non Overlapped Clock Pulse Shift Register Design

Research Area: Volume 6,Issue 3, May 2017 Year: 2017
Type of Publication: Article Keywords: CMOS, Pulse Latch, Power Dissipation, Area Optimization
Authors:
  • Ajaz Ahmad
  • Nikhil Ranjan
Journal: IJEIR Volume: 6
Number: 3 Pages: 137-140
Month: May
ISSN: 2277-5668
Abstract:
This paper discusses the area and power optimization of shift register. The shift register is design using edge triggered flip flops. The use of latch in shift register creates timing problems which can be avoided by using pulse clock base latches as a basic cell in shift register. This resolve the timing problem created in shift register by using several non overlapping clock in a duration of pulses. This also reduces the number of cells which in turn reduces area of circuit. The shift register cell CMOS layout is design using 50nm technology in MICROWIND layout simulator tool.

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