Reducing Power, Leakage of Standard-Cell Design using Stack Transistor Logic Design

Research Area: Volume 7,Issue 2, March 2018 Year: 2018
Type of Publication: Article Keywords: Stack Transistor, MOS, Transmission Gate, Layout Design, Leakage Power
Authors:
  • Richa Singh
  • Dilip Ahirwar
Journal: IJEIR Volume: 7
Number: 2 Pages: 88-91
Month: March
ISSN: 2277-5668
Abstract:
In this paper, a low leakage power optimizes CMOS layout designs. The approach is base on series-connected stack transistor technique. At first, the basic logic gate with conventional CMOS design and stack transistor base logic gate design is discussed. In stack technique, a two reduce size transistors are series connected with both gate terminals are interconnected to form single input

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