Low Power Area Efficient Reverse Converter Design Via Parallel Prefix Adder

Research Area: Volume 6,Issue 6,Nov.,2017 Year: 2017
Type of Publication: Article Keywords: Digital Arithmetic, Parallel-Prefix Adder, Residue Number System RNS, Reverse Converter
Authors:
  • Akanksha Gautam
  • Sandeep Nemade
Journal: IJEIR Volume: 6
Number: 6 Pages: 251-253
Month: November
ISSN: 2277-5668
Abstract:
The implementation of residue number system reverse converters based on well-known regular and modular parallel prefix adders is analyzed. The VLSI implementation results show a significant delay reduction and area × time2 improvements, all this at the cost of higher power consumption, which is the main reason preventing the use of parallel-prefix adders to achieve high-speed reverse converters in nowadays systems. Hence, to solve the high power consumption problem, novel specific hybrid parallel-prefix-based adder components those provide better tradeoff between delay and power consumption. The power, area and delay of the proposed system are analysis using Xilinx 14.2

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