The phase locked loop (PLL) is primary requirement for the synchronous communication system, because the clock synchronization is must for proper data receptions. In such systems the synchronization is performed by PLL. This paper presents a new design for the fast locking digital PLL which reduced the locking time greatly. The paper also presents the simulated results of the proposed DPLL in mixed signal environment by using VHDL-AMS. The VHDL-AMS is used here because of simplicity & its capability to perform the simulation of systems that contains both analog and digital components. Finally the simulation result shows that the proposed model performs well.

Full text: IJEIR-319-FINAL.pdf