The design of high-speed, area-efficient and low power multiplier is essential for the VLSI implementation of DSP systems. In many applications, like digital filtering, the inputs are contaminated by noise and precise outputs are often not required. A new high precision serial multiplier with most significant digit first is presented. This method uses a borrow save adder to perform the reduction of large length partial products required by the multiplications of large numbers. The results are converted from Borrow-Save (BS) form to 2’s complement representation by the on the fly conversion which let the conversion of the digit result as soon as it is obtained. the comparison between the residual and these constants (-3/2, -1/2, 1/2 and 3/2) needed in the radix-2 on line multiplication, present problem in high precision computation. In the proposed method the operands are introduced digit by digit with Most Significant Digit First (MSDF) mode and results are obtained in the same manner with fixed time delay independently of the operand size. So this approach is advantageously used for the long multiplication computation. The results of the implementations of this multiplier for several operands sizes on Virtex-II. FPGA circuit confirms that the multiplication is performed in constant time.

Full text: IJEIR_633_Final.pdf