This study presents a unified electrical model for a Nanoscale FDSOIMOSFET with a channel thickness as low as 1.6 nm. The experimental I-V Transfer Characteristics are anomalous in the linear region. This phenomenon is modeled by a huge parasitic drain-source series resistance, dependent on the gate voltage. Moreover the gate leakage current is included in this generic model. Additional methods, like CV and Rm-L, were used to indicate the origin of the series resistance. The generic analytical approach developed in this model can be useful for the Nano-Scale Body (NSB) devices modeling, where such phenomena are of great reliability concern to guide Failure Analysis (FA) of FDSOI MOSFET and Transistor-like Nanoscale Devices Regime.

Full text: IJEIR_790_Final.pdf