Modern wireless communication systems are designed to be multi-mode and use different algorithms to implement forward error correction decoding. Sharing of Datapath and Memories across different FEC families and also across different standards of one FEC family are of paramount importance. In this paper we analyze the hardware reuse of datapath across different possibilities of the implemented architecture. First a serial implementation scheme of Min-Sum algorithm for LDPC decoding is explored over Max-Log-Map based turbo decoder datapath architecture. The implementation results are presented, showing that different possibilities may at most give a reduction of around 14% in combined datapath area. Secondly, We propose a novel Parallel implementation scheme for Min-sum algorithm which fits very well with underline turbo decoding architecture, and show that the proposed scheme not only provides significant speed-up in terms of clock cycles for VN updates, but also results in a reduction of around 24.5% in combined datapath area.

Full text: IJEIR-360_final.pdf