As MOSFET dimensions shrink to the nanometre scale, the leakage power and negative-bias temperature instability (NBTI) become a challenging issue. Leakage power can be decrease by Stack transistor, Sleep transistor and transmission gate base techniques. Sleep transistor technique provided lesser static power dissipation and lesser static power delay product in comparison with the other techniques. It has been shown previously that the stacking of two off transistors has significantly reduced sub-threshold leakage compared to a single off transistor. In this work a stack transistor technique using two series connected stack is use to design the digital circuit. But it has a delay penalty. The static and dynamic power of stack is considerably low. But it has a delay penalty and its area requirement is maximum compared with other processes. This can be overcome by using stack transistors of half size. Our goal is to trade off between these limitations and thus propose new methods which reduce both leakage and dynamic power with minimum possible area and delay trade off.

Full text: IJEIR_1515_Final.pdf